The present invention relates generally to communications on a single chip, and more particularly, to a technique for transmitting multiple-level signals on each wire of the single chip.
Address and data busses provide data paths that are shared by a number of data processing devices, such as memory devices, micro-controllers, microprocessors, digital signal processors (DSPs) and peripheral devices. Busses are typically formed on printed circuit boards (PCBs) and interconnect the various devices mounted on the PCB. The busses may also extend to connectors in order to allow external devices to be coupled to the bus.
Recently, integrated circuit (IC) manufacturers have begun producing single chips containing multiple device cores, such as multiple memory devices, micro-controllers, microprocessors and digital signal processors, that were traditionally mounted on a PCB and interconnected by one or more busses on the PCB. Such a single chip is commonly referred to as a system-on-a-chip (SoC). SoCs incorporate one or more busses to provide data paths to interconnect the multiple core devices on the chip, often referred to as xe2x80x9cnodes.xe2x80x9d The busses on SoCs, however, comprise conductor traces on the chip and thus tend to be much shorter in length than PCB busses.
As SoCs grow in size and complexity, the requirement of communicating control and data signals between various nodes or devices on the SoC becomes more difficult, primarily due to the resistive-capacitive (RC) delays attributed to the conductor length. To meet customer expectations for increasing performance, DSP and microprocessor architects are adopting wider buses for address and data signals used to communicate with memory and peripheral devices. Consequently, the area and power required for these buses to operate can become a very significant portion of the total device size (cost) and power budget.
A need therefore exists for a method and apparatus for transmitting additional data on a chip without increasing the bus width or power dissipation. A number of techniques have been proposed or suggested in the data transmission domain for improving transmission performance. Computer modem devices operating in the 1200 to 9600 bits-per-second (baud) range, for example, convert short strings of digital bits into phase or amplitude modulated sinusoidal carrier signals (or both). Thus, multiple bits may be converted to quadrature phase-shift modulation of various frequency sinusoids and the carrier signal may be transmitted long distances without losing its information content. While this technique performs well for long distance transmissions, it is not well suited to on-chip environment of the present invention. Specifically, the length of the wire trace is shorter than the required wavelength and the signal cannot modulate.
10BASE-T Ethernet systems use a bit-serial transmission scheme over twisted pairs to transmit data over distances on the order of 100 meters. The data is represented by current transitions that are coupled on-to and off-of the line through transformers. Within one bit interval, the data value is represented as either one transition or two transitions. For example, a high-to-low transition might represent the value zero (0), while a low-to-high-to-low transition pair might represent the value one (1). The guaranteed presence of transitions makes clock recovery possible and hence provides reliable data recovery. While this technique performs well for transmissions of reasonably long length, it is not well-suited to on-chip environment of the present invention. Specifically, the inductive coupling of signals onto the transmission line associated with the 10BASE-T Ethernet standard would be difficult to achieve in normal CMOS processing.
Discrete voltage levels have been used to store information. One example of a multi-level storage system is a 2 bits-per-cell dynamic random access memory (DRAM) from Toshiba, as described in Betty Prince, xe2x80x9cSemiconductor Memories,xe2x80x9d 334 (1989). Each cell stores one of four voltage (charge) levels to record two bits of information. The output of the cell is compared in parallel with three reference levels positioned at the mid-range points to determine the stored value. A second example of a multi-level charge storage system is the StrataFlash non-volatile memory technology from Intel Corp. The StrataFlash memory also stores 2 bits-per-cell using four voltage (charge) levels.
These existing multi-level memory devices demonstrate that CMOS circuits can be built to reliably detect at least four voltage levels. Both memories use reference voltages and sense amplifiers to discriminate voltage levels that are proportional to the stored charge. In a memory, each sense amplifier is shared by many storage cells, and the number of outputs is relatively small, on the order of 1 or 4 outputs for a DRAM and 8 or 16 outputs for a Flash electronically erasable programmable read only memory (EEPROM). For a SoC bus application, however, the bus may be 128 or more bits wide, and each receiving module would need a set of sense amplifiers. Hence, linear sense amplifiers may not be practical for a bus application because of the high active power dissipation.
Generally, a method and apparatus are disclosed for transmitting multiple bits among nodes on a chip using quantized voltage levels. Each node on the chip includes a multiple level logic bus driver and receiver for communicating over a bus using a multiple-level logic protocol in accordance with the present invention. The multiple-level logic protocol transfers multiple bits on each signal wire of the bus in a given time interval without increasing the bus width or power dissipation.
In an exemplary embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e.g., 1.2V or 1.3V) power supplies (Vdd) and P and N transistor threshold voltage levels of Vtp and Vtn on the order of 0.4-0.5V. Thus, the separation between each voltage level is approximately uniform. The exemplary quad logic level quantization divides the supply voltage level into approximately 3 equal parts such that the gap between each logic level becomes 0.4V to 0.5V in the exemplary embodiment. Thus, four logic levels are established as follows: Vdd; Vddxe2x88x92Vtp; Vss+Vtn; and Vss.
The lower supply voltages employed by the present invention provide two inherent advantages, compared to a higher power supply (over 2V). First, the approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. Second, since the absolute magnitude of the coupling noise is much lower, it requires less active power to recover from an AC injected noise source. In addition, the number of physical wires on the bus can be reduced by at least half for the same number of bits transferred. The present invention also reduces the total transmission power by more than fifty percent (50%) since some of the signal transitions are less than rail-to-rail.
A bus noise minimization scheme and a quick recovery scheme are also disclosed to ensure the correct data transfer in the presence of injected noise. The disclosed quad logic level bus driver includes a high impedance equalizer transistor that serves as a noise minimizer and allows quick recovery from an injected noise transient. Another aspect of the invention, provides an initial over drive for shorter transition times. One characteristic of transistor circuits employing low power supply voltages (i.e., Vdd approximately equal to 3Vt) is that the voltage level of logic xcex1 and xcex2 states are very close to the N and P transistor threshold voltage levels (Vtnand Vddxe2x88x92Vtp, respectively). Thus, when logic a is driven on a bus wire, the receiver would not be able to quickly distinguish the a logic level from logic xe2x80x980xe2x80x99 (VSS). Therefore, to overcome this problem and to ensure quick data transfer, the circuit portion of this invention includes a data over driver circuit within the bus driver such that, when the data on the bus changes from 1 or 0 to either xcex1 or xcex2 the over drive circuit becomes active and drives the bus wire with Vss+Vtn (or Vddxe2x88x92Vtp).
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.